Merging upstream version 0.7.1 (Closes: #991419).
Signed-off-by: Daniel Baumann <daniel@debian.org>
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99 changed files with 6727 additions and 943 deletions
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@ -58,8 +58,8 @@
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#endif
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/*
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* Prevent speculative execution in busy-wait loops (P4 <=)
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* or "predefined delay".
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* Prevent speculative execution in busy-wait loops (P4 <=) or "predefined
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* delay".
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*/
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CK_CC_INLINE static void
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ck_pr_stall(void)
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@ -75,18 +75,39 @@ ck_pr_stall(void)
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__asm__ __volatile__(I ::: "memory"); \
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}
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CK_PR_FENCE(atomic, "sfence")
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CK_PR_FENCE(atomic_store, "sfence")
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CK_PR_FENCE(atomic_load, "mfence")
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CK_PR_FENCE(store_atomic, "sfence")
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CK_PR_FENCE(load_atomic, "mfence")
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/* Atomic operations are always serializing. */
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CK_PR_FENCE(atomic, "")
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CK_PR_FENCE(atomic_store, "")
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CK_PR_FENCE(atomic_load, "")
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CK_PR_FENCE(store_atomic, "")
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CK_PR_FENCE(load_atomic, "")
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/* Traditional fence interface. */
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CK_PR_FENCE(load, "lfence")
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CK_PR_FENCE(load_store, "mfence")
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CK_PR_FENCE(store, "sfence")
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CK_PR_FENCE(store_load, "mfence")
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CK_PR_FENCE(memory, "mfence")
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/* Below are stdatomic-style fences. */
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/*
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* Provides load-store and store-store ordering. However, Intel specifies that
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* the WC memory model is relaxed. It is likely an sfence *is* sufficient (in
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* particular, stores are not re-ordered with respect to prior loads and it is
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* really just the stores that are subject to re-ordering). However, we take
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* the conservative route as the manuals are too ambiguous for my taste.
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*/
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CK_PR_FENCE(release, "mfence")
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/*
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* Provides load-load and load-store ordering. The lfence instruction ensures
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* all prior load operations are complete before any subsequent instructions
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* actually begin execution. However, the manual also ends up going to describe
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* WC memory as a relaxed model.
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*/
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CK_PR_FENCE(acquire, "mfence")
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CK_PR_FENCE(acqrel, "mfence")
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CK_PR_FENCE(lock, "mfence")
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CK_PR_FENCE(unlock, "mfence")
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@ -311,18 +332,18 @@ CK_PR_FAA_S(8, uint8_t, "xaddb")
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}
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#define CK_PR_UNARY_V(K, S, T, C, I) \
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CK_CC_INLINE static void \
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ck_pr_##K##_##S##_zero(T *target, bool *r) \
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CK_CC_INLINE static bool \
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ck_pr_##K##_##S##_is_zero(T *target) \
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{ \
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bool ret; \
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__asm__ __volatile__(CK_PR_LOCK_PREFIX I " %0; setz %1" \
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: "+m" (*(C *)target), \
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"=m" (*r) \
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"=rm" (ret) \
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: \
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: "memory", "cc"); \
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return; \
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return ret; \
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}
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#define CK_PR_UNARY_S(K, S, T, I) CK_PR_UNARY(K, S, T, T, I)
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#define CK_PR_GENERATE(K) \
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@ -387,8 +408,38 @@ CK_PR_GENERATE(xor)
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#undef CK_PR_BINARY
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/*
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* Atomic compare and swap.
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* Atomic compare and swap, with a variant that sets *v to the old value of target.
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*/
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#ifdef __GCC_ASM_FLAG_OUTPUTS__
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#define CK_PR_CAS(S, M, T, C, I) \
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CK_CC_INLINE static bool \
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ck_pr_cas_##S(M *target, T compare, T set) \
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{ \
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bool z; \
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__asm__ __volatile__(CK_PR_LOCK_PREFIX I " %3, %0" \
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: "+m" (*(C *)target), \
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"=@ccz" (z), \
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/* RAX is clobbered by cmpxchg. */ \
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"+a" (compare) \
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: "q" (set) \
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: "memory", "cc"); \
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return z; \
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} \
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\
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CK_CC_INLINE static bool \
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ck_pr_cas_##S##_value(M *target, T compare, T set, M *v) \
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{ \
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bool z; \
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__asm__ __volatile__(CK_PR_LOCK_PREFIX I " %3, %0;" \
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: "+m" (*(C *)target), \
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"=@ccz" (z), \
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"+a" (compare) \
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: "q" (set) \
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: "memory", "cc"); \
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*(T *)v = compare; \
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return z; \
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}
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#else
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#define CK_PR_CAS(S, M, T, C, I) \
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CK_CC_INLINE static bool \
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ck_pr_cas_##S(M *target, T compare, T set) \
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@ -401,7 +452,23 @@ CK_PR_GENERATE(xor)
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"a" (compare) \
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: "memory", "cc"); \
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return z; \
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} \
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\
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CK_CC_INLINE static bool \
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ck_pr_cas_##S##_value(M *target, T compare, T set, M *v) \
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{ \
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bool z; \
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__asm__ __volatile__(CK_PR_LOCK_PREFIX I " %3, %0;" \
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"setz %1;" \
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: "+m" (*(C *)target), \
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"=q" (z), \
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"+a" (compare) \
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: "q" (set) \
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: "memory", "cc"); \
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*(T *)v = compare; \
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return z; \
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}
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#endif
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CK_PR_CAS(ptr, void, void *, char, "cmpxchgq")
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@ -421,45 +488,6 @@ CK_PR_CAS_S(8, uint8_t, "cmpxchgb")
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#undef CK_PR_CAS_S
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#undef CK_PR_CAS
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/*
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* Compare and swap, set *v to old value of target.
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*/
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#define CK_PR_CAS_O(S, M, T, C, I, R) \
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CK_CC_INLINE static bool \
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ck_pr_cas_##S##_value(M *target, T compare, T set, M *v) \
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{ \
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bool z; \
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__asm__ __volatile__(CK_PR_LOCK_PREFIX "cmpxchg" I " %3, %0;" \
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"mov %% " R ", %2;" \
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"setz %1;" \
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: "+m" (*(C *)target), \
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"=a" (z), \
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"=m" (*(C *)v) \
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: "q" (set), \
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"a" (compare) \
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: "memory", "cc"); \
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return z; \
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}
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CK_PR_CAS_O(ptr, void, void *, char, "q", "rax")
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#define CK_PR_CAS_O_S(S, T, I, R) \
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CK_PR_CAS_O(S, T, T, T, I, R)
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CK_PR_CAS_O_S(char, char, "b", "al")
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CK_PR_CAS_O_S(int, int, "l", "eax")
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CK_PR_CAS_O_S(uint, unsigned int, "l", "eax")
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#ifndef CK_PR_DISABLE_DOUBLE
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CK_PR_CAS_O_S(double, double, "q", "rax")
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#endif
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CK_PR_CAS_O_S(64, uint64_t, "q", "rax")
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CK_PR_CAS_O_S(32, uint32_t, "l", "eax")
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CK_PR_CAS_O_S(16, uint16_t, "w", "ax")
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CK_PR_CAS_O_S(8, uint8_t, "b", "al")
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#undef CK_PR_CAS_O_S
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#undef CK_PR_CAS_O
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/*
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* Contrary to C-interface, alignment requirements are that of uint64_t[2].
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*/
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