Adding upstream version 1.65.7.
Signed-off-by: Daniel Baumann <daniel@debian.org>
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4153 changed files with 2487292 additions and 0 deletions
139
internal/overlay/musl/arch/arm/atomic_arch.h
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139
internal/overlay/musl/arch/arm/atomic_arch.h
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@ -0,0 +1,139 @@
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#include "libc.h"
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#if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
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#define BLX "mov lr,pc\n\tbx"
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#else
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#define BLX "blx"
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#endif
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extern hidden uintptr_t __a_cas_ptr, __a_barrier_ptr;
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#if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
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|| __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define a_ll a_ll
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static inline int a_ll(volatile int *p)
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#ifndef __CCGO__
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{
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int v;
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__asm__ __volatile__ ("ldrex %0, %1" : "=r"(v) : "Q"(*p));
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return v;
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}
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#else
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;
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#endif
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#define a_sc a_sc
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static inline int a_sc(volatile int *p, int v)
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#ifndef __CCGO__
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{
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int r;
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__asm__ __volatile__ ("strex %0,%2,%1" : "=&r"(r), "=Q"(*p) : "r"(v) : "memory");
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return !r;
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}
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#else
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;
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#endif
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#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define a_barrier a_barrier
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static inline void a_barrier()
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#ifndef __CCGO__
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{
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__asm__ __volatile__ ("dmb ish" : : : "memory");
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}
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#else
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;
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#endif
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#endif
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#define a_pre_llsc a_barrier
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#define a_post_llsc a_barrier
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#else
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#define a_cas a_cas
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static inline int a_cas(volatile int *p, int t, int s)
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#ifndef __CCGO__
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{
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for (;;) {
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register int r0 __asm__("r0") = t;
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register int r1 __asm__("r1") = s;
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register volatile int *r2 __asm__("r2") = p;
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register uintptr_t r3 __asm__("r3") = __a_cas_ptr;
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int old;
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__asm__ __volatile__ (
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BLX " r3"
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: "+r"(r0), "+r"(r3) : "r"(r1), "r"(r2)
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: "memory", "lr", "ip", "cc" );
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if (!r0) return t;
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if ((old=*p)!=t) return old;
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}
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}
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#else
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;
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#endif
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#endif
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#ifndef a_barrier
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#define a_barrier a_barrier
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static inline void a_barrier()
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#ifndef __CCGO__
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{
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register uintptr_t ip __asm__("ip") = __a_barrier_ptr;
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__asm__ __volatile__( BLX " ip" : "+r"(ip) : : "memory", "cc", "lr" );
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}
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#else
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;
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#endif
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#endif
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#define a_crash a_crash
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static inline void a_crash()
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#ifndef __CCGO__
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{
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__asm__ __volatile__(
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#ifndef __thumb__
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".word 0xe7f000f0"
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#else
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".short 0xdeff"
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#endif
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: : : "memory");
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}
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#else
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;
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#endif
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#if __ARM_ARCH >= 5 && (!__thumb__ || __thumb2__)
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#define a_clz_32 a_clz_32
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static inline int a_clz_32(uint32_t x)
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#ifndef __CCGO__
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{
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__asm__ ("clz %0, %1" : "=r"(x) : "r"(x));
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return x;
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}
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#else
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;
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#endif
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#if __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define a_ctz_32 a_ctz_32
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static inline int a_ctz_32(uint32_t x)
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#ifndef __CCGO__
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{
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uint32_t xr;
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__asm__ ("rbit %0, %1" : "=r"(xr) : "r"(x));
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return a_clz_32(xr);
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}
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#else
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;
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#endif
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#endif
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#endif
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16
internal/overlay/musl/arch/arm/bits/float.h
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16
internal/overlay/musl/arch/arm/bits/float.h
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@ -0,0 +1,16 @@
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#define FLT_EVAL_METHOD 0
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#define LDBL_TRUE_MIN 4.94065645841246544177e-324L
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#define LDBL_MIN 2.22507385850720138309e-308L
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#define LDBL_MAX 1.79769313486231570815e+308L
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#define LDBL_EPSILON 2.22044604925031308085e-16L
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#define LDBL_MANT_DIG 53
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#define LDBL_MIN_EXP (-1021)
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#define LDBL_MAX_EXP 1024
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#define LDBL_DIG 15
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#define LDBL_MIN_10_EXP (-307)
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#define LDBL_MAX_10_EXP 308
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#define DECIMAL_DIG 17
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36
internal/overlay/musl/arch/arm/pthread_arch.h
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36
internal/overlay/musl/arch/arm/pthread_arch.h
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@ -0,0 +1,36 @@
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static inline uintptr_t __get_tp();
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#ifndef __CCGO__
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#if ((__ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
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|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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static inline uintptr_t __get_tp()
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{
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uintptr_t tp;
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__asm__ ( "mrc p15,0,%0,c13,c0,3" : "=r"(tp) );
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return tp;
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}
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#else
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#if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
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#define BLX "mov lr,pc\n\tbx"
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#else
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#define BLX "blx"
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#endif
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static inline uintptr_t __get_tp()
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{
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extern hidden uintptr_t __a_gettp_ptr;
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register uintptr_t tp __asm__("r0");
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__asm__ ( BLX " %1" : "=r"(tp) : "r"(__a_gettp_ptr) : "cc", "lr" );
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return tp;
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}
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#endif
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#endif
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#define TLS_ABOVE_TP
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#define GAP_ABOVE_TP 8
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#define MC_PC arm_pc
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127
internal/overlay/musl/arch/arm/syscall_arch.h
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127
internal/overlay/musl/arch/arm/syscall_arch.h
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@ -0,0 +1,127 @@
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#ifdef __CCGO__
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static __inline long __syscall0(long n);
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static __inline long __syscall1(long n, long a1);
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static __inline long __syscall2(long n, long a1, long a2);
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static __inline long __syscall3(long n, long a1, long a2, long a3);
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static __inline long __syscall4(long n, long a1, long a2, long a3, long a4);
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static __inline long __syscall5(long n, long a1, long a2, long a3, long a4, long a5);
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static __inline long __syscall6(long n, long a1, long a2, long a3, long a4, long a5, long a6);
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#define __SYSCALL_LL_E(x) ((int)(x)), ((int)((x)>>32))
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#define __SYSCALL_LL_O(x) 0, __SYSCALL_LL_E((x))
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#else // __CCGO__
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#define __SYSCALL_LL_E(x) \
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((union { long long ll; long l[2]; }){ .ll = x }).l[0], \
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((union { long long ll; long l[2]; }){ .ll = x }).l[1]
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#define __SYSCALL_LL_O(x) 0, __SYSCALL_LL_E((x))
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#ifdef __thumb__
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/* Avoid use of r7 in asm constraints when producing thumb code,
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* since it's reserved as frame pointer and might not be supported. */
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#define __ASM____R7__
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#define __asm_syscall(...) do { \
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__asm__ __volatile__ ( "mov %1,r7 ; mov r7,%2 ; svc 0 ; mov r7,%1" \
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: "=r"(r0), "=&r"((int){0}) : __VA_ARGS__ : "memory"); \
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return r0; \
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} while (0)
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#else
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#define __ASM____R7__ __asm__("r7")
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#define __asm_syscall(...) do { \
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__asm__ __volatile__ ( "svc 0" \
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: "=r"(r0) : __VA_ARGS__ : "memory"); \
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return r0; \
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} while (0)
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#endif
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/* For thumb2, we can allow 8-bit immediate syscall numbers, saving a
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* register in the above dance around r7. Does not work for thumb1 where
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* only movs, not mov, supports immediates, and we can't use movs because
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* it doesn't support high regs. */
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#ifdef __thumb2__
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#define R7_OPERAND "rI"(r7)
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#else
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#define R7_OPERAND "r"(r7)
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#endif
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static inline long __syscall0(long n)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0");
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__asm_syscall(R7_OPERAND);
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}
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static inline long __syscall1(long n, long a)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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__asm_syscall(R7_OPERAND, "0"(r0));
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}
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static inline long __syscall2(long n, long a, long b)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1));
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}
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static inline long __syscall3(long n, long a, long b, long c)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2));
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}
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static inline long __syscall4(long n, long a, long b, long c, long d)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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register long r3 __asm__("r3") = d;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3));
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}
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static inline long __syscall5(long n, long a, long b, long c, long d, long e)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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register long r3 __asm__("r3") = d;
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register long r4 __asm__("r4") = e;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3), "r"(r4));
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}
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static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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register long r3 __asm__("r3") = d;
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register long r4 __asm__("r4") = e;
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register long r5 __asm__("r5") = f;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3), "r"(r4), "r"(r5));
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}
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#define SYSCALL_IPC_BROKEN_MODE
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#define VDSO_USEFUL
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#define VDSO_CGT32_SYM "__vdso_clock_gettime"
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#define VDSO_CGT32_VER "LINUX_2.6"
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#define VDSO_CGT_SYM "__vdso_clock_gettime64"
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#define VDSO_CGT_VER "LINUX_2.6"
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#define VDSO_CGT_WORKAROUND 1
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#endif // __CCGO__
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#define SYSCALL_FADVISE_6_ARG
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