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# Intel PowerStat Input Plugin
This plugin gathers power statistics on Intel-based platforms providing insights
into power saving and workload migration. Those are beneficial for Monitoring
and Analytics systems to take preventive or corrective actions based on platform
busyness, CPU temperature, actual CPU utilization and power statistics.
⭐ Telegraf v1.17.0
🏷️ hardware, system
💻 linux
## Requirements
### Kernel modules
Plugin is mostly based on Linux Kernel modules that expose specific metrics over
`sysfs` or `devfs` interfaces. The following dependencies are expected:
- `intel-rapl` kernel module which exposes Intel Runtime Power Limiting metrics over
`sysfs` (`/sys/devices/virtual/powercap/intel-rapl`),
- `msr` kernel module that provides access to processor model specific
registers over `devfs` (`/dev/cpu/cpu%d/msr`),
- `cpufreq` kernel module - which exposes per-CPU Frequency over `sysfs`
(`/sys/devices/system/cpu/cpu%d/cpufreq/scaling_cur_freq`),
- `intel-uncore-frequency` kernel module exposes Intel uncore frequency metrics
over `sysfs` (`/sys/devices/system/cpu/intel_uncore_frequency`).
Make sure the required kernel modules are loaded and running. Modules might have
to be manually enabled by using `modprobe`. Depending on the kernel version,
run the following commands:
```sh
# rapl modules:
## kernel < 4.0
sudo modprobe intel_rapl
## kernel >= 4.0
sudo modprobe rapl
sudo modprobe intel_rapl_common
sudo modprobe intel_rapl_msr
# msr module:
sudo modprobe msr
# cpufreq module:
### integrated in kernel
# intel-uncore-frequency module:
## only for kernel >= 5.6.0
sudo modprobe intel-uncore-frequency
```
### Kernel's perf interface
For perf-related metrics, when Telegraf is not running as root, the following
capability should be added to the Telegraf executable:
```sh
sudo setcap cap_sys_admin+ep <path_to_telegraf_binary>
```
Alternatively, `/proc/sys/kernel/perf_event_paranoid` has to be set to value
less than 1.
Depending on environment and configuration (number of monitored CPUs and number
of enabled metrics), it might be required to increase the limit on the number of
open file descriptors allowed. This can be done for example by using `ulimit -n`
command.
### Root privileges
> [!IMPORTANT]
> Telegraf with Intel PowerStat plugin enabled may require root privileges to
> read all the metrics (depending on OS type or configuration).
Alternatively, the following capabilities can be added to the Telegraf
executable:
```sh
#without perf-related metrics:
sudo setcap cap_sys_rawio,cap_dac_read_search+ep <path_to_telegraf_binary>
#with perf-related metrics:
sudo setcap cap_sys_rawio,cap_dac_read_search,cap_sys_admin+ep <path_to_telegraf_binary>
```
### Supported hardware
Specific metrics require certain processor features to be present, otherwise
Intel PowerStat plugin won't be able to read them. The user can detect supported
processor features by reading `/proc/cpuinfo` file.
Plugin assumes crucial properties are the same for all CPU cores in the system.
The following `processor` properties are examined in more detail
in this section:
- `vendor_id`
- `cpu family`
- `model`
- `flags`
The following processor properties are required by the plugin:
- Processor `vendor_id` must be `GenuineIntel` and `cpu family` must be `6` -
since data used by the plugin are Intel-specific.
- The following processor flags shall be present:
- `msr` shall be present for plugin to read platform data from processor
model specific registers and collect the following metrics:
- `cpu_c0_state_residency`
- `cpu_c1_state_residency`
- `cpu_c3_state_residency`
- `cpu_c6_state_residency`
- `cpu_c7_state_residency`
- `cpu_busy_cycles` (**DEPRECATED** - superseded by `cpu_c0_state_residency_percent`)
- `cpu_busy_frequency`
- `cpu_temperature`
- `cpu_base_frequency`
- `max_turbo_frequency`
- `uncore_frequency` (for kernel < 5.18)
- `aperfmperf` shall be present to collect the following metrics:
- `cpu_c0_state_residency`
- `cpu_c1_state_residency`
- `cpu_busy_cycles` (**DEPRECATED** - superseded by `cpu_c0_state_residency_percent`)
- `cpu_busy_frequency`
- `dts` shall be present to collect:
- `cpu_temperature`
- supported CPU model. To see which metrics are supported by your `model`. The
following metrics exist:
- `cpu_c1_state_residency`
- `cpu_c3_state_residency`
- `cpu_c6_state_residency`
- `cpu_c7_state_residency`
- `cpu_temperature`
- `cpu_base_frequency`
- `uncore_frequency`
### Supported CPU models
| Model number | Processor name | `cpu_c1_state_residency`<br/>`cpu_c6_state_residency`<br/>`cpu_temperature`<br/>`cpu_base_frequency` | `cpu_c3_state_residency` | `cpu_c7_state_residency` | `uncore_frequency` |
|--------------|---------------------------------|:----------------------------------------------------------------------------------------------------:|:------------------------:|:------------------------:|:------------------:|
| 0x1E | Intel Nehalem | ✓ | ✓ | | |
| 0x1F | Intel Nehalem-G | ✓ | ✓ | | |
| 0x1A | Intel Nehalem-EP | ✓ | ✓ | | |
| 0x2E | Intel Nehalem-EX | ✓ | ✓ | | |
| 0x25 | Intel Westmere | ✓ | ✓ | | |
| 0x2C | Intel Westmere-EP | ✓ | ✓ | | |
| 0x2F | Intel Westmere-EX | ✓ | ✓ | | |
| 0x2A | Intel Sandybridge | ✓ | ✓ | ✓ | |
| 0x2D | Intel Sandybridge-X | ✓ | ✓ | ✓ | |
| 0x3A | Intel Ivybridge | ✓ | ✓ | ✓ | |
| 0x3E | Intel Ivybridge-X | ✓ | ✓ | ✓ | |
| 0x3C | Intel Haswell | ✓ | ✓ | ✓ | |
| 0x3F | Intel Haswell-X | ✓ | ✓ | ✓ | |
| 0x45 | Intel Haswell-L | ✓ | ✓ | ✓ | |
| 0x46 | Intel Haswell-G | ✓ | ✓ | ✓ | |
| 0x3D | Intel Broadwell | ✓ | ✓ | ✓ | |
| 0x47 | Intel Broadwell-G | ✓ | ✓ | ✓ | ✓ |
| 0x4F | Intel Broadwell-X | ✓ | ✓ | | ✓ |
| 0x56 | Intel Broadwell-D | ✓ | ✓ | | ✓ |
| 0x4E | Intel Skylake-L | ✓ | ✓ | ✓ | |
| 0x5E | Intel Skylake | ✓ | ✓ | ✓ | |
| 0x55 | Intel Skylake-X | ✓ | | | ✓ |
| 0x8E | Intel KabyLake-L | ✓ | ✓ | ✓ | |
| 0x9E | Intel KabyLake | ✓ | ✓ | ✓ | |
| 0xA5 | Intel CometLake | ✓ | ✓ | ✓ | |
| 0xA6 | Intel CometLake-L | ✓ | ✓ | ✓ | |
| 0x66 | Intel CannonLake-L | ✓ | | ✓ | |
| 0x6A | Intel IceLake-X | ✓ | | | ✓ |
| 0x6C | Intel IceLake-D | ✓ | | | ✓ |
| 0x7D | Intel IceLake | ✓ | | | |
| 0x7E | Intel IceLake-L | ✓ | | ✓ | |
| 0x9D | Intel IceLake-NNPI | ✓ | | ✓ | |
| 0xA7 | Intel RocketLake | ✓ | | ✓ | |
| 0x8C | Intel TigerLake-L | ✓ | | ✓ | |
| 0x8D | Intel TigerLake | ✓ | | ✓ | |
| 0x8F | Intel Sapphire Rapids X | ✓ | | | ✓ |
| 0xCF | Intel Emerald Rapids X | ✓ | | | ✓ |
| 0xAD | Intel Granite Rapids X | ✓ | | | |
| 0xAE | Intel Granite Rapids D | ✓ | | | |
| 0x8A | Intel Lakefield | ✓ | | ✓ | |
| 0x97 | Intel AlderLake | ✓ | | ✓ | ✓ |
| 0x9A | Intel AlderLake-L | ✓ | | ✓ | ✓ |
| 0xB7 | Intel RaptorLake | ✓ | | ✓ | ✓ |
| 0xBA | Intel RaptorLake-P | ✓ | | ✓ | ✓ |
| 0xBF | Intel RaptorLake-S | ✓ | | ✓ | ✓ |
| 0xAC | Intel MeteorLake | ✓ | | ✓ | ✓ |
| 0xAA | Intel MeteorLake-L | ✓ | | ✓ | ✓ |
| 0xC6 | Intel ArrowLake | ✓ | | ✓ | |
| 0xBD | Intel LunarLake | ✓ | | ✓ | |
| 0x37 | Intel Atom® Bay Trail | ✓ | | | |
| 0x4D | Intel Atom® Avaton | ✓ | | | |
| 0x4A | Intel Atom® Merrifield | ✓ | | | |
| 0x5A | Intel Atom® Moorefield | ✓ | | | |
| 0x4C | Intel Atom® Airmont | ✓ | ✓ | | |
| 0x5C | Intel Atom® Apollo Lake | ✓ | ✓ | ✓ | |
| 0x5F | Intel Atom® Denverton | ✓ | | | |
| 0x7A | Intel Atom® Goldmont | ✓ | ✓ | ✓ | |
| 0x86 | Intel Atom® Jacobsville | ✓ | | | |
| 0x96 | Intel Atom® Elkhart Lake | ✓ | | ✓ | |
| 0x9C | Intel Atom® Jasper Lake | ✓ | | ✓ | |
| 0xBE | Intel AlderLake-N | ✓ | | ✓ | |
| 0xAF | Intel Sierra Forest | ✓ | | | |
| 0xB6 | Intel Grand Ridge | ✓ | | | |
| 0x57 | Intel Xeon® PHI Knights Landing | ✓ | | | |
| 0x85 | Intel Xeon® PHI Knights Mill | ✓ | | | |
## Global configuration options <!-- @/docs/includes/plugin_config.md -->
In addition to the plugin-specific configuration settings, plugins support
additional global and plugin configuration settings. These settings are used to
modify metrics, tags, and field or create aliases and configure ordering, etc.
See the [CONFIGURATION.md][CONFIGURATION.md] for more details.
[CONFIGURATION.md]: ../../../docs/CONFIGURATION.md#plugins
## Configuration
```toml @sample.conf
# Intel PowerStat plugin enables monitoring of platform metrics (power, TDP)
# and per-CPU metrics like temperature, power and utilization. Please see the
# plugin readme for details on software and hardware compatibility.
# This plugin ONLY supports Linux.
[[inputs.intel_powerstat]]
## The user can choose which package metrics are monitored by the plugin with
## the package_metrics setting:
## - The default, will collect "current_power_consumption",
## "current_dram_power_consumption" and "thermal_design_power".
## - Leaving this setting empty means no package metrics will be collected.
## - Finally, a user can specify individual metrics to capture from the
## supported options list.
## Supported options:
## "current_power_consumption", "current_dram_power_consumption",
## "thermal_design_power", "max_turbo_frequency", "uncore_frequency",
## "cpu_base_frequency"
# package_metrics = ["current_power_consumption", "current_dram_power_consumption", "thermal_design_power"]
## The user can choose which per-CPU metrics are monitored by the plugin in
## cpu_metrics array.
## Empty or missing array means no per-CPU specific metrics will be collected
## by the plugin.
## Supported options:
## "cpu_frequency", "cpu_c0_state_residency", "cpu_c1_state_residency",
## "cpu_c3_state_residency", "cpu_c6_state_residency", "cpu_c7_state_residency",
## "cpu_temperature", "cpu_busy_frequency", "cpu_c0_substate_c01",
## "cpu_c0_substate_c02", "cpu_c0_substate_c0_wait"
# cpu_metrics = []
## CPUs metrics to include from those configured in cpu_metrics array
## Can't be combined with excluded_cpus. Empty means all CPUs are gathered.
## e.g. ["0-3", "4,5,6"] or ["1-3,4"]
# included_cpus = []
## CPUs metrics to exclude from those configured in cpu_metrics array
## Can't be combined with included_cpus. Empty means all CPUs are gathered.
## e.g. ["0-3", "4,5,6"] or ["1-3,4"]
# excluded_cpus = []
## Filesystem location of JSON file that contains PMU event definitions.
## Mandatory only for perf-related metrics (cpu_c0_substate_c01, cpu_c0_substate_c02, cpu_c0_substate_c0_wait).
# event_definitions = ""
## The user can set the timeout duration for MSR reading.
## Enabling this timeout can be useful in situations where, on heavily loaded systems,
## the code waits too long for a kernel response to MSR read requests.
## 0 disables the timeout (default).
# msr_read_timeout = "0ms"
```
1. The configuration of `included_cpus` or `excluded_cpus` may affect the
ability to collect `package_metrics`. Some of them
(`max_turbo_frequency`, `cpu_base_frequency`, and `uncore_frequency`) need to
read data from exactly one processor for each package. If `included_cpus` or
`excluded_cpus` exclude all processors from the package, reading th
mentioned metrics for that package will not be possible.
2. `event_definitions` JSON file for specific architecture can be found at
[perfmon][perfmon]. A script to download the event definition that is
appropriate for current environment (`event_download.py`) is available at
[pmu-tools][pmu_tools]. For perf-related metrics supported by this plugin,
an event definition JSON file with events for the `core` is required, e.g.
`sapphirerapids_core.json` or `GenuineIntel-6-8F-core.json`.
[perfmon]: https://github.com/intel/perfmon
[pmu_tools]: https://github.com/andikleen/pmu-tools
### Dependencies of metrics on system configuration
Details of these dependencies are discussed above:
| Configuration option | Type | Dependency |
|--------------------------------------------------------------------------|-------------------|-------------------|
| `current_power_consumption` | `package_metrics` | `rapl` module |
| `current_dram_power_consumption` | `package_metrics` | `rapl` module |
| `thermal_design_power` | `package_metrics` | `rapl` module |
| `max_turbo_frequency` | `package_metrics` | `msr` module |
| `uncore_frequency` | `package_metrics` | `intel-uncore-frequency` module* |
| `cpu_base_frequency` | `package_metrics` | `msr` module |
| `cpu_frequency` | `cpu_metrics` | `cpufreq` module |
| `cpu_c0_state_residency` | `cpu_metrics` | `msr` module |
| `cpu_c1_state_residency` | `cpu_metrics` | `msr` module |
| `cpu_c3_state_residency` | `cpu_metrics` | `msr` module |
| `cpu_c6_state_residency` | `cpu_metrics` | `msr` module |
| `cpu_c7_state_residency` | `cpu_metrics` | `msr` module |
| `cpu_busy_cycles` (**DEPRECATED**, use `cpu_c0_state_residency_percent`) | `cpu_metrics` | `msr` module |
| `cpu_temperature` | `cpu_metrics` | `msr` module |
| `cpu_busy_frequency` | `cpu_metrics` | `msr` module |
| `cpu_c0_substate_c01` | `cpu_metrics` | `perf` interface |
| `cpu_c0_substate_c02` | `cpu_metrics` | `perf` interface |
| `cpu_c0_substate_c0_wait` | `cpu_metrics` | `perf` interface |
*for all metrics enabled by the configuration option `uncore_frequency`,
starting from kernel version 5.18, only the `intel-uncore-frequency` module
is required. For older kernel versions, the metric `uncore_frequency_mhz_cur`
requires the `msr` module to be enabled.
### Example: Configuration with no per-CPU telemetry
This configuration allows getting default processor package specific metrics,
no per-CPU metrics are collected:
```toml
[[inputs.intel_powerstat]]
cpu_metrics = []
```
### Example: Configuration with no per-CPU telemetry - equivalent case
This configuration allows getting default processor package specific metrics,
no per-CPU metrics are collected:
```toml
[[inputs.intel_powerstat]]
```
### Example: Configuration for CPU Temperature and CPU Frequency
This configuration allows getting default processor package specific metrics,
plus subset of per-CPU metrics (CPU Temperature and CPU Frequency) which will be
gathered only for `cpu_id = 0`:
```toml
[[inputs.intel_powerstat]]
cpu_metrics = ["cpu_frequency", "cpu_temperature"]
included_cpus = ["0"]
```
### Example: Configuration for CPU Temperature and CPU Frequency without default package metrics
This configuration allows getting only a subset of per-CPU metrics
(CPU Temperature and CPU Frequency) which will be gathered for
all `cpus` except `cpu_id = ["1-3"]`:
```toml
[[inputs.intel_powerstat]]
package_metrics = []
cpu_metrics = ["cpu_frequency", "cpu_temperature"]
excluded_cpus = ["1-3"]
```
### Example: Configuration with all available metrics
This configuration allows getting all processor package specific metrics and
all per-CPU metrics:
```toml
[[inputs.intel_powerstat]]
package_metrics = ["current_power_consumption", "current_dram_power_consumption", "thermal_design_power", "max_turbo_frequency", "uncore_frequency", "cpu_base_frequency"]
cpu_metrics = ["cpu_frequency", "cpu_c0_state_residency", "cpu_c1_state_residency", "cpu_c3_state_residency", "cpu_c6_state_residency", "cpu_c7_state_residency", "cpu_temperature", "cpu_busy_frequency", "cpu_c0_substate_c01", "cpu_c0_substate_c02", "cpu_c0_substate_c0_wait"]
event_definitions = "/home/telegraf/.cache/pmu-events/GenuineIntel-6-8F-core.json"
```
## Metrics
All metrics collected by Intel PowerStat plugin are collected in fixed
intervals. Metrics that reports processor C-state residency or power are
calculated over elapsed intervals.
The following measurements are supported by Intel PowerStat plugin:
- `powerstat_core`
- The following tags are returned by plugin with
`powerstat_core` measurements:
| Tag | Description |
|--------------|--------------------------------|
| `package_id` | ID of platform package/socket. |
| `core_id` | ID of physical processor core. |
| `cpu_id` | ID of logical processor core. |
Measurement `powerstat_core` metrics are collected per-CPU (`cpu_id` is the key)
while `core_id` and `package_id` tags are additional topology information.
- Available metrics for `powerstat_core` measurement:
| Metric name (field) | Description | Units |
|-----------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------|
| `cpu_frequency_mhz` | Current operational frequency of CPU Core. | MHz |
| `cpu_busy_frequency_mhz` | CPU Core Busy Frequency measured as frequency adjusted to CPU Core busy cycles. | MHz |
| `cpu_temperature_celsius` | Current temperature of CPU Core. | Celsius degrees |
| `cpu_c0_state_residency_percent` | Percentage of time that CPU Core spent in C0 Core residency state. | % |
| `cpu_c1_state_residency_percent` | Percentage of time that CPU Core spent in C1 Core residency state. | % |
| `cpu_c3_state_residency_percent` | Percentage of time that CPU Core spent in C3 Core residency state. | % |
| `cpu_c6_state_residency_percent` | Percentage of time that CPU Core spent in C6 Core residency state. | % |
| `cpu_c7_state_residency_percent` | Percentage of time that CPU Core spent in C7 Core residency state. | % |
| `cpu_c0_substate_c01_percent` | Percentage of time that CPU Core spent in C0.1 substate out of the total time in the C0 state. | % |
| `cpu_c0_substate_c02_percent` | Percentage of time that CPU Core spent in C0.2 substate out of the total time in the C0 state. | % |
| `cpu_c0_substate_c0_wait_percent` | Percentage of time that CPU Core spent in C0_Wait substate out of the total time in the C0 state. | % |
| `cpu_busy_cycles_percent` | (**DEPRECATED** - superseded by cpu_c0_state_residency_percent) CPU Core Busy cycles as a ratio of Cycles spent in C0 state residency to all cycles executed by CPU Core. | % |
- `powerstat_package`
- The following tags are returned by plugin with `powerstat_package` measurements:
| Tag | Description |
|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| `package_id` | ID of platform package/socket. |
| `active_cores` | Specific tag for `max_turbo_frequency_mhz` metric. The maximum number of activated cores for reachable turbo frequency. |
| `hybrid` | Specific tag for `max_turbo_frequency_mhz` metric. Available only for hybrid processors. Will be set to `primary` for primary cores of a hybrid architecture, and to `secondary` for secondary cores of a hybrid architecture. |
| `die` | Specific tag for all `uncore_frequency` metrics. Id of die. |
| `type` | Specific tag for all `uncore_frequency` metrics. Type of uncore frequency (`current` or `initial`). |
Measurement `powerstat_package` metrics are collected per processor package
`package_id` tag indicates which package metric refers to.
- Available metrics for `powerstat_package` measurement:
| Metric name (field) | Description | Units |
|----------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------|
| `thermal_design_power_watts` | Maximum Thermal Design Power (TDP) available for processor package. | Watts |
| `current_power_consumption_watts` | Current power consumption of processor package. | Watts |
| `current_dram_power_consumption_watts` | Current power consumption of processor package DRAM subsystem. | Watts |
| `max_turbo_frequency_mhz` | Maximum reachable turbo frequency for number of cores active. | MHz |
| `uncore_frequency_limit_mhz_min` | Minimum uncore frequency limit for die in processor package. | MHz |
| `uncore_frequency_limit_mhz_max` | Maximum uncore frequency limit for die in processor package. | MHz |
| `uncore_frequency_mhz_cur` | Current uncore frequency for die in processor package. Available only with tag `current`. This value is available from `intel-uncore-frequency` module for kernel >= 5.18. For older kernel versions it needs to be accessed via MSR. In case of lack of loaded `msr`, only `uncore_frequency_limit_mhz_min` and `uncore_frequency_limit_mhz_max` metrics will be collected. | MHz |
| `cpu_base_frequency_mhz` | CPU Base Frequency (maximum non-turbo frequency) for the processor package. | MHz |
### Known issues
Starting from Linux kernel version v5.4.77, due to
[this kernel change][19f6d91b], resources such as
`/sys/devices/virtual/powercap/intel-rapl//*/energy_uj`
can only be accessed by the root user for security reasons.
Therefore, this plugin requires root privileges to gather
`rapl` metrics correctly.
If such strict security restrictions are not relevant, reading permissions for
files in the `/sys/devices/virtual/powercap/intel-rapl/` directory can be
manually altered, for example, using the chmod command with custom parameters.
For instance, read and execute permissions for all files in the
intel-rapl directory can be granted to all users using:
```bash
sudo chmod -R a+rx /sys/devices/virtual/powercap/intel-rapl/
```
[19f6d91b]: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.4.77&id=19f6d91bdad42200aac557a683c17b1f65ee6c94
## Example Output
```text
powerstat_package,host=ubuntu,package_id=0 thermal_design_power_watts=160 1606494744000000000
powerstat_package,host=ubuntu,package_id=0 current_power_consumption_watts=35 1606494744000000000
powerstat_package,host=ubuntu,package_id=0 cpu_base_frequency_mhz=2400i 1669118424000000000
powerstat_package,host=ubuntu,package_id=0 current_dram_power_consumption_watts=13.94 1606494744000000000
powerstat_package,host=ubuntu,package_id=0,active_cores=0 max_turbo_frequency_mhz=3000i 1606494744000000000
powerstat_package,host=ubuntu,package_id=0,active_cores=1 max_turbo_frequency_mhz=2800i 1606494744000000000
powerstat_package,die=0,host=ubuntu,package_id=0,type=initial uncore_frequency_limit_mhz_min=800,uncore_frequency_limit_mhz_max=2400 1606494744000000000
powerstat_package,die=0,host=ubuntu,package_id=0,type=current uncore_frequency_mhz_cur=800i,uncore_frequency_limit_mhz_min=800,uncore_frequency_limit_mhz_max=2400 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_frequency_mhz=1200.29 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_temperature_celsius=34i 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c0_state_residency_percent=0.8 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c1_state_residency_percent=6.68 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c3_state_residency_percent=0 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c6_state_residency_percent=92.52 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c7_state_residency_percent=0 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_busy_frequency_mhz=1213.24 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c0_substate_c01_percent=0 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c0_substate_c02_percent=5.68 1606494744000000000
powerstat_core,core_id=0,cpu_id=0,host=ubuntu,package_id=0 cpu_c0_substate_c0_wait_percent=43.74 1606494744000000000
```

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//go:build linux && amd64
package intel_powerstat
import (
ptel "github.com/intel/powertelemetry"
)
// topologyFetcher fetches topology information of the host.
type topologyFetcher interface {
// GetMsrCPUIDs returns a slice with available CPU IDs of the host for which msr will access to.
GetMsrCPUIDs() []int
// GetPerfCPUIDs returns a slice with available CPU IDs of the host for which perf will access to.
GetPerfCPUIDs() []int
// GetPackageIDs returns a slice with available package IDs of the host.
GetPackageIDs() []int
// GetCPUPackageID returns the package ID of the host corresponding to the given CPU ID.
GetCPUPackageID(cpuID int) (int, error)
// GetCPUCoreID returns the core ID of the host corresponding to the given CPU ID.
GetCPUCoreID(cpuID int) (int, error)
// GetPackageDieIDs returns the die IDs of the host corresponding to the given package ID.
GetPackageDieIDs(packageID int) ([]int, error)
}
// cpuFreqFetcher fetches supported CPU-related metrics relying on core frequency.
type cpuFreqFetcher interface {
// GetCPUFrequency returns the current frequency value of a given CPU ID, in MHz.
GetCPUFrequency(cpuID int) (float64, error)
}
// cpuMsrFetcher fetches supported CPU-related metrics relying on msr registers.
type cpuMsrFetcher interface {
// GetCPUTemperature returns the temperature value of a given CPU ID, in degrees Celsius.
GetCPUTemperature(cpuID int) (uint64, error)
// UpdatePerCPUMetrics reads multiple MSR offsets needed to get metric values that are time sensitive.
// Below are the list of methods that need the update to be performed beforehand.
UpdatePerCPUMetrics(cpuID int) error
// GetCPUC0StateResidency returns the C0 state residency value of a given CPU ID, as a percentage.
GetCPUC0StateResidency(cpuID int) (float64, error)
// GetCPUC1StateResidency returns the C1 state residency value of a given CPU ID, as a percentage.
GetCPUC1StateResidency(cpuID int) (float64, error)
// GetCPUC3StateResidency returns the C3 state residency value of a given CPU ID, as a percentage.
GetCPUC3StateResidency(cpuID int) (float64, error)
// GetCPUC6StateResidency returns the C6 state residency value of a given CPU ID, as a percentage.
GetCPUC6StateResidency(cpuID int) (float64, error)
// GetCPUC7StateResidency returns the C7 state residency value of a given CPU ID, as a percentage.
GetCPUC7StateResidency(cpuID int) (float64, error)
// GetCPUBusyFrequencyMhz returns the busy frequency value of a given CPU ID, in MHz.
GetCPUBusyFrequencyMhz(cpuID int) (float64, error)
}
// cpuPerfFetcher fetches supported CPU-related metrics relying on perf events.
type cpuPerfFetcher interface {
// ReadPerfEvents reads values of perf events needed to get C0X state residency metrics.
// Below getter methods that need this operation to be performed previously.
ReadPerfEvents() error
// DeactivatePerfEvents deactivates perf events. It closes file descriptors used to get perf event values.
DeactivatePerfEvents() error
// GetCPUC0SubstateC01Percent takes a CPU ID and returns a value indicating the percentage of time
// the processor spent in its C0.1 substate out of the total time in the C0 state.
// C0.1 is characterized by a light-weight slower wakeup time but more power-saving optimized state.
GetCPUC0SubstateC01Percent(cpuID int) (float64, error)
// GetCPUC0SubstateC02Percent takes a CPU ID and returns a value indicating the percentage of time
// the processor spent in its C0.2 substate out of the total time in the C0 state.
// C0.2 is characterized by a light-weight faster wakeup time but less power saving optimized state.
GetCPUC0SubstateC02Percent(cpuID int) (float64, error)
// GetCPUC0SubstateC0WaitPercent takes a CPU ID and returns a value indicating the percentage of time
// the processor spent in its C0_Wait substate out of the total time in the C0 state.
// CPU is in C0_Wait substate when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.
GetCPUC0SubstateC0WaitPercent(cpuID int) (float64, error)
}
// packageRaplFetcher fetches supported package related metrics relying on rapl.
type packageRaplFetcher interface {
// GetCurrentPackagePowerConsumptionWatts returns the current package power consumption value of a given package ID, in watts.
GetCurrentPackagePowerConsumptionWatts(packageID int) (float64, error)
// GetCurrentDramPowerConsumptionWatts returns the current dram power consumption value of a given package ID, in watts.
GetCurrentDramPowerConsumptionWatts(packageID int) (float64, error)
// GetPackageThermalDesignPowerWatts returns the thermal power design value of a given package ID, in watts.
GetPackageThermalDesignPowerWatts(packageID int) (float64, error)
}
// packageUncoreFreqFetcher fetches supported package related metrics relying on uncore frequency.
type packageUncoreFreqFetcher interface {
// GetInitialUncoreFrequencyMin returns the minimum initial uncore frequency value of a given package ID, in MHz.
GetInitialUncoreFrequencyMin(packageID, dieID int) (float64, error)
// GetInitialUncoreFrequencyMax returns the maximum initial uncore frequency value of a given package ID, in MHz.
GetInitialUncoreFrequencyMax(packageID, dieID int) (float64, error)
// GetCustomizedUncoreFrequencyMin returns the minimum custom uncore frequency value of a given package ID, in MHz.
GetCustomizedUncoreFrequencyMin(packageID, dieID int) (float64, error)
// GetCustomizedUncoreFrequencyMax returns the maximum custom uncore frequency value of a given package ID, in MHz.
GetCustomizedUncoreFrequencyMax(packageID, dieID int) (float64, error)
// GetCurrentUncoreFrequency returns the current uncore frequency value of a given package ID, in MHz.
GetCurrentUncoreFrequency(packageID, dieID int) (float64, error)
}
// packageMsrFetcher fetches supported package related metrics relying on msr registers.
type packageMsrFetcher interface {
// GetCPUBaseFrequency returns the CPU base frequency value of a given package ID, in MHz.
GetCPUBaseFrequency(packageID int) (uint64, error)
// GetMaxTurboFreqList returns a list of max turbo frequencies and related active cores of a given package ID.
GetMaxTurboFreqList(packageID int) ([]ptel.MaxTurboFreq, error)
}
// metricFetcher fetches metrics supported by this plugin.
type metricFetcher interface {
topologyFetcher
cpuFreqFetcher
cpuMsrFetcher
cpuPerfFetcher
packageRaplFetcher
packageUncoreFreqFetcher
packageMsrFetcher
}

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//go:generate ../../../tools/readme_config_includer/generator
//go:build !linux || !amd64
package intel_powerstat
import (
_ "embed"
"github.com/influxdata/telegraf"
"github.com/influxdata/telegraf/plugins/inputs"
)
//go:embed sample.conf
var sampleConfig string
type IntelPowerstat struct {
Log telegraf.Logger `toml:"-"`
}
func (*IntelPowerstat) SampleConfig() string { return sampleConfig }
func (i *IntelPowerstat) Init() error {
i.Log.Warn("Current platform is not supported")
return nil
}
func (*IntelPowerstat) Gather(_ telegraf.Accumulator) error { return nil }
func init() {
inputs.Add("intel_powerstat", func() telegraf.Input {
return &IntelPowerstat{}
})
}

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//go:build linux && amd64
package intel_powerstat
import (
"errors"
"fmt"
"math"
"strconv"
ptel "github.com/intel/powertelemetry"
"github.com/influxdata/telegraf"
)
// cpuMetricType is an enum type to identify core metrics.
type cpuMetricType int
// cpuMetricType enum defines supported core metrics.
const (
// metric relying on cpuFreq
cpuFrequency cpuMetricType = iota
// metric relying on msr
cpuTemperature
// metrics relying on msr with storage
cpuC0StateResidency
cpuC1StateResidency
cpuC3StateResidency
cpuC6StateResidency
cpuC7StateResidency
cpuBusyCycles // alias of cpuC0StateResidency
cpuBusyFrequency
// metrics relying on perf
cpuC0SubstateC01Percent
cpuC0SubstateC02Percent
cpuC0SubstateC0WaitPercent
)
// Helper method to return a string representation of a core metric.
func (m cpuMetricType) String() string {
switch m {
case cpuFrequency:
return "cpu_frequency"
case cpuTemperature:
return "cpu_temperature"
case cpuBusyFrequency:
return "cpu_busy_frequency"
case cpuC0StateResidency:
return "cpu_c0_state_residency"
case cpuC1StateResidency:
return "cpu_c1_state_residency"
case cpuC3StateResidency:
return "cpu_c3_state_residency"
case cpuC6StateResidency:
return "cpu_c6_state_residency"
case cpuC7StateResidency:
return "cpu_c7_state_residency"
case cpuBusyCycles:
return "cpu_busy_cycles"
case cpuC0SubstateC01Percent:
return "cpu_c0_substate_c01"
case cpuC0SubstateC02Percent:
return "cpu_c0_substate_c02"
case cpuC0SubstateC0WaitPercent:
return "cpu_c0_substate_c0_wait"
}
return ""
}
// UnmarshalText parses the cpu metric from the TOML config file
func (m *cpuMetricType) UnmarshalText(data []byte) (err error) {
parsedMetric, err := cpuMetricTypeFromString(string(data))
if err != nil {
return err
}
*m = parsedMetric
return nil
}
func cpuMetricTypeFromString(metric string) (cpuMetricType, error) {
switch metric {
case "cpu_frequency":
return cpuFrequency, nil
case "cpu_temperature":
return cpuTemperature, nil
case "cpu_busy_frequency":
return cpuBusyFrequency, nil
case "cpu_c0_state_residency":
return cpuC0StateResidency, nil
case "cpu_c1_state_residency":
return cpuC1StateResidency, nil
case "cpu_c3_state_residency":
return cpuC3StateResidency, nil
case "cpu_c6_state_residency":
return cpuC6StateResidency, nil
case "cpu_c7_state_residency":
return cpuC7StateResidency, nil
case "cpu_busy_cycles":
return cpuBusyCycles, nil
case "cpu_c0_substate_c01":
return cpuC0SubstateC01Percent, nil
case "cpu_c0_substate_c02":
return cpuC0SubstateC02Percent, nil
case "cpu_c0_substate_c0_wait":
return cpuC0SubstateC0WaitPercent, nil
}
return -1, fmt.Errorf("invalid cpu metric specified: %q", metric)
}
// packageMetricType is an enum type to identify package metrics.
type packageMetricType int
// packageMetricType enum defines supported package metrics.
const (
// metrics relying on rapl
packageCurrentPowerConsumption packageMetricType = iota
packageCurrentDramPowerConsumption
packageThermalDesignPower
// metrics relying on msr
packageCPUBaseFrequency
// hybrid metric relying on uncoreFreq as a primary mechanism and on msr as fallback mechanism.
packageUncoreFrequency
// metrics relying on msr
packageTurboLimit
)
// Helper method to return a string representation of a package metric.
func (m packageMetricType) String() string {
switch m {
case packageCurrentPowerConsumption:
return "current_power_consumption"
case packageCurrentDramPowerConsumption:
return "current_dram_power_consumption"
case packageThermalDesignPower:
return "thermal_design_power"
case packageCPUBaseFrequency:
return "cpu_base_frequency"
case packageUncoreFrequency:
return "uncore_frequency"
case packageTurboLimit:
return "max_turbo_frequency"
}
return ""
}
// UnmarshalText parses the package metric from the TOML config file
func (m *packageMetricType) UnmarshalText(data []byte) (err error) {
parsedMetric, err := packageMetricTypeFromString(string(data))
if err != nil {
return err
}
*m = parsedMetric
return nil
}
func packageMetricTypeFromString(metric string) (packageMetricType, error) {
switch metric {
case "current_power_consumption":
return packageCurrentPowerConsumption, nil
case "current_dram_power_consumption":
return packageCurrentDramPowerConsumption, nil
case "thermal_design_power":
return packageThermalDesignPower, nil
case "cpu_base_frequency":
return packageCPUBaseFrequency, nil
case "uncore_frequency":
return packageUncoreFrequency, nil
case "max_turbo_frequency":
return packageTurboLimit, nil
}
return -1, fmt.Errorf("invalid package metric specified: %q", metric)
}
// numeric is a type constraint definition.
type numeric interface {
float64 | uint64
}
// metricInfoProvider provides measurement name, fields, and tags needed by the accumulator to add a metric.
type metricInfoProvider interface {
// measurement returns a string with the name of measurement.
measurement() string
// fields returns a map of string keys with metric name and metric values.
fields() (map[string]interface{}, error)
// tags returns a map of string key and string value to add additional metric-specific information.
tags() map[string]string
// name returns the name of a metric.
name() string
}
// addMetric takes a metricInfoProvider interface and adds metric information to an accumulator.
func addMetric(acc telegraf.Accumulator, m metricInfoProvider, logOnceMap map[string]struct{}) {
fields, err := m.fields()
if err == nil {
acc.AddGauge(
m.measurement(),
fields,
m.tags(),
)
return
}
// Always add to the accumulator errors not related to module not initialized.
var moduleErr *ptel.ModuleNotInitializedError
if !errors.As(err, &moduleErr) {
acc.AddError(err)
return
}
// Add only once module not initialized error related to module and metric name.
logErrorOnce(
acc,
logOnceMap,
fmt.Sprintf("%s_%s", moduleErr.Name, m.name()),
fmt.Errorf("failed to get %q: %w", m.name(), moduleErr),
)
}
// metricCommon has metric information common to different types.
type metricCommon struct {
metric interface{}
units string
}
func (m *metricCommon) name() string {
switch m.metric.(type) {
case cpuMetricType:
return m.metric.(cpuMetricType).String()
case packageMetricType:
return m.metric.(packageMetricType).String()
default:
return ""
}
}
func (m *metricCommon) measurement() string {
switch m.metric.(type) {
case cpuMetricType:
return "powerstat_core"
case packageMetricType:
return "powerstat_package"
default:
return ""
}
}
// cpuMetric is a generic type that has the information to identify a CPU-related metric,
// as well as function to retrieve its value at any time. Implements metricAdder interface.
type cpuMetric[T numeric] struct {
metricCommon
cpuID int
coreID int
packageID int
fetchFn func(cpuID int) (T, error)
}
func (m *cpuMetric[T]) fields() (map[string]interface{}, error) {
val, err := m.fetchFn(m.cpuID)
if err != nil {
return nil, fmt.Errorf("failed to get %q for CPU ID %v: %w", m.metric, m.cpuID, err)
}
return map[string]interface{}{
fmt.Sprintf("%s_%s", m.metric, m.units): round(val),
}, nil
}
func (m *cpuMetric[T]) tags() map[string]string {
return map[string]string{
"core_id": strconv.Itoa(m.coreID),
"cpu_id": strconv.Itoa(m.cpuID),
"package_id": strconv.Itoa(m.packageID),
}
}
// packageMetric is a generic type that has the information to identify a package-related metric,
// as well as the function to retrieve its value at any time. Implements metricAdder interface.
type packageMetric[T numeric] struct {
metricCommon
packageID int
fetchFn func(packageID int) (T, error)
}
func (m *packageMetric[T]) fields() (map[string]interface{}, error) {
val, err := m.fetchFn(m.packageID)
if err != nil {
return nil, fmt.Errorf("failed to get %q for package ID %v: %w", m.metric, m.packageID, err)
}
return map[string]interface{}{
fmt.Sprintf("%s_%s", m.metric, m.units): round(val),
}, nil
}
func (m *packageMetric[T]) tags() map[string]string {
return map[string]string{
"package_id": strconv.Itoa(m.packageID),
}
}
// round returns the result of rounding the argument, only if it's a 64 bit floating-point type.
func round[T numeric](val T) T {
if v, ok := any(val).(float64); ok {
val = T(math.Round(v*100) / 100)
}
return val
}

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//go:build linux && amd64
package intel_powerstat
import (
"testing"
"github.com/stretchr/testify/require"
)
func TestCoreMetric_String(t *testing.T) {
testCases := []struct {
name string
metricName string
}{
{
name: "CPUFrequency",
metricName: "cpu_frequency",
},
{
name: "CPUTemperature",
metricName: "cpu_temperature",
},
{
name: "CPUC0StateResidency",
metricName: "cpu_c0_state_residency",
},
{
name: "CPUC1StateResidency",
metricName: "cpu_c1_state_residency",
},
{
name: "CPUC3StateResidency",
metricName: "cpu_c3_state_residency",
},
{
name: "CPUC6StateResidency",
metricName: "cpu_c6_state_residency",
},
{
name: "CPUC7StateResidency",
metricName: "cpu_c7_state_residency",
},
{
name: "CPUBusyCycles",
metricName: "cpu_busy_cycles",
},
{
name: "CPUBusyFrequency",
metricName: "cpu_busy_frequency",
},
{
name: "CPUC0SubstateC01Percent",
metricName: "cpu_c0_substate_c01",
},
{
name: "CPUC0SubstateC02Percent",
metricName: "cpu_c0_substate_c02",
},
{
name: "CPUC0SubstateC0WaitPercent",
metricName: "cpu_c0_substate_c0_wait",
},
{
name: "Invalid",
metricName: "",
},
}
for i, tc := range testCases {
t.Run(tc.name, func(t *testing.T) {
metric := cpuMetricType(i)
require.Equal(t, tc.metricName, metric.String())
})
}
}
func TestPackageMetric_String(t *testing.T) {
testCases := []struct {
name string
metricName string
}{
{
name: "PackageCurrentPowerConsumption",
metricName: "current_power_consumption",
},
{
name: "PackageCurrentDramPowerConsumption",
metricName: "current_dram_power_consumption",
},
{
name: "PackageThermalDesignPower",
metricName: "thermal_design_power",
},
{
name: "PackageCPUBaseFrequency",
metricName: "cpu_base_frequency",
},
{
name: "PackageUncoreFrequency",
metricName: "uncore_frequency",
},
{
name: "PackageTurboLimit",
metricName: "max_turbo_frequency",
},
{
name: "Invalid",
metricName: "",
},
}
for i, tc := range testCases {
t.Run(tc.name, func(t *testing.T) {
metric := packageMetricType(i)
require.Equal(t, tc.metricName, metric.String())
})
}
}
func TestCPUMetricTypeFromString(t *testing.T) {
t.Run("Valid", func(t *testing.T) {
for m := cpuMetricType(0); m < cpuC0SubstateC0WaitPercent+1; m++ {
val, err := cpuMetricTypeFromString(m.String())
require.NoError(t, err)
require.Equal(t, m, val)
}
})
t.Run("Invalid", func(t *testing.T) {
val, err := cpuMetricTypeFromString("invalid")
require.Error(t, err)
require.Equal(t, cpuMetricType(-1), val)
})
}
func TestPackageMetricTypeFromString(t *testing.T) {
t.Run("Valid", func(t *testing.T) {
for m := packageMetricType(0); m < packageTurboLimit+1; m++ {
val, err := packageMetricTypeFromString(m.String())
require.NoError(t, err)
require.Equal(t, m, val)
}
})
t.Run("Invalid", func(t *testing.T) {
val, err := packageMetricTypeFromString("invalid")
require.Error(t, err)
require.Equal(t, packageMetricType(-1), val)
})
}

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//go:build linux && amd64
package intel_powerstat
import (
"slices"
"time"
ptel "github.com/intel/powertelemetry"
"github.com/influxdata/telegraf"
)
// optConfig represents plugin configuration fields needed to generate options.
type optConfig struct {
cpuMetrics []cpuMetricType
packageMetrics []packageMetricType
includedCPUs []int
excludedCPUs []int
perfEventFile string
msrReadTimeout time.Duration
log telegraf.Logger
}
// optionGenerator takes a struct with the plugin configuration, and generates options
// needed to gather metrics.
type optionGenerator interface {
generate(cfg optConfig) []ptel.Option
}
// optGenerator implements optionGenerator interface.
type optGenerator struct{}
// generate takes plugin configuration options and generates options needed
// to gather requested metrics.
func (*optGenerator) generate(cfg optConfig) []ptel.Option {
opts := make([]ptel.Option, 0)
if len(cfg.includedCPUs) != 0 {
opts = append(opts, ptel.WithIncludedCPUs(cfg.includedCPUs))
}
if len(cfg.excludedCPUs) != 0 {
opts = append(opts, ptel.WithExcludedCPUs(cfg.excludedCPUs))
}
if needsMsrCPU(cfg.cpuMetrics) || needsMsrPackage(cfg.packageMetrics) {
if cfg.msrReadTimeout == 0 {
opts = append(opts, ptel.WithMsr())
} else {
opts = append(opts, ptel.WithMsrTimeout(cfg.msrReadTimeout))
}
}
if needsRapl(cfg.packageMetrics) {
opts = append(opts, ptel.WithRapl())
}
if needsCoreFreq(cfg.cpuMetrics) {
opts = append(opts, ptel.WithCoreFrequency())
}
if needsUncoreFreq(cfg.packageMetrics) {
opts = append(opts, ptel.WithUncoreFrequency())
}
if needsPerf(cfg.cpuMetrics) {
opts = append(opts, ptel.WithPerf(cfg.perfEventFile))
}
if cfg.log != nil {
opts = append(opts, ptel.WithLogger(cfg.log))
}
return opts
}
// needsMsr takes a slice of strings, representing supported metrics, and
// returns true if any relies on msr registers.
func needsMsrCPU(metrics []cpuMetricType) bool {
for _, m := range metrics {
switch m {
case cpuTemperature:
case cpuC0StateResidency:
case cpuC1StateResidency:
case cpuC3StateResidency:
case cpuC6StateResidency:
case cpuC7StateResidency:
case cpuBusyCycles:
case cpuBusyFrequency:
default:
continue
}
return true
}
return false
}
// needsMsrPackage takes a slice of strings, representing supported metrics, and
// returns true if any relies on msr registers.
func needsMsrPackage(metrics []packageMetricType) bool {
for _, m := range metrics {
switch m {
case packageCPUBaseFrequency:
case packageTurboLimit:
case packageUncoreFrequency:
// Fallback mechanism retrieves this metric from MSR registers.
default:
continue
}
return true
}
return false
}
// needsTimeRelatedMsr takes a slice of strings, representing supported metrics, and
// returns true if any relies on time-related reads of msr registers.
func needsTimeRelatedMsr(metrics []cpuMetricType) bool {
for _, m := range metrics {
switch m {
case cpuC0StateResidency:
case cpuC1StateResidency:
case cpuC3StateResidency:
case cpuC6StateResidency:
case cpuC7StateResidency:
case cpuBusyCycles:
case cpuBusyFrequency:
default:
continue
}
return true
}
return false
}
// needsRapl takes a slice of strings, representing supported metrics, and
// returns true if any relies on intel-rapl control zone.
func needsRapl(metrics []packageMetricType) bool {
for _, m := range metrics {
switch m {
case packageCurrentPowerConsumption:
case packageCurrentDramPowerConsumption:
case packageThermalDesignPower:
default:
continue
}
return true
}
return false
}
// needsCoreFreq takes a slice of strings, representing supported metrics, and
// returns true if any relies on sysfs "/sys/devices/system/cpu/" with global and
// individual CPU attributes.
func needsCoreFreq(metrics []cpuMetricType) bool {
return slices.Contains(metrics, cpuFrequency)
}
// needsUncoreFreq takes a slice of strings, representing supported metrics, and returns
// true if any relies on sysfs interface "/sys/devices/system/cpu/intel_uncore_frequency/"
// provided by intel_uncore_frequency kernel module.
func needsUncoreFreq(metrics []packageMetricType) bool {
return slices.Contains(metrics, packageUncoreFrequency)
}
// needsPerf takes a slice of strings, representing supported metrics, and
// returns true if any relies on perf_events interface.
func needsPerf(metrics []cpuMetricType) bool {
for _, m := range metrics {
switch m {
case cpuC0SubstateC01Percent:
case cpuC0SubstateC02Percent:
case cpuC0SubstateC0WaitPercent:
default:
continue
}
return true
}
return false
}

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//go:build linux && amd64
package intel_powerstat
import (
"reflect"
"runtime"
"strings"
"testing"
"time"
"github.com/stretchr/testify/require"
"github.com/influxdata/telegraf/testutil"
)
func TestGenerate(t *testing.T) {
t.Run("NoCPUsSpecified", func(t *testing.T) {
g := &optGenerator{}
opts := g.generate(optConfig{
cpuMetrics: []cpuMetricType{
cpuFrequency, // needs coreFreq
cpuC0SubstateC01Percent, // needs perf
},
packageMetrics: []packageMetricType{
packageCurrentPowerConsumption, // needs rapl
packageUncoreFrequency, // needs uncoreFreq and msr
},
})
require.Len(t, opts, 5)
})
t.Run("ExcludedCPUs", func(t *testing.T) {
g := &optGenerator{}
opts := g.generate(optConfig{
excludedCPUs: []int{0, 1, 2, 3},
cpuMetrics: []cpuMetricType{
// needs msr
cpuTemperature,
},
packageMetrics: []packageMetricType{
// needs rapl
packageCurrentPowerConsumption,
},
})
require.Len(t, opts, 3)
})
t.Run("IncludedCPUs", func(t *testing.T) {
g := &optGenerator{}
opts := g.generate(optConfig{
includedCPUs: []int{0, 1, 2, 3},
cpuMetrics: []cpuMetricType{
cpuFrequency, // needs coreFreq
cpuC0SubstateC0WaitPercent, // needs perf
},
packageMetrics: []packageMetricType{
packageTurboLimit, // needs msr
packageCurrentDramPowerConsumption, // needs rapl
packageUncoreFrequency, // needs uncoreFreq
},
})
require.Len(t, opts, 6)
})
t.Run("WithMsrTimeout", func(t *testing.T) {
g := &optGenerator{}
opts := g.generate(optConfig{
cpuMetrics: []cpuMetricType{
cpuTemperature,
},
msrReadTimeout: time.Second,
})
require.Len(t, opts, 1)
withMsrTimeoutUsed := false
for _, opt := range opts {
if strings.Contains(runtime.FuncForPC(reflect.ValueOf(opt).Pointer()).Name(), ".WithMsrTimeout.") {
withMsrTimeoutUsed = true
continue
}
}
require.True(t, withMsrTimeoutUsed, "WithMsrTimeout wasn't included in the generated options")
})
t.Run("WithMsr", func(t *testing.T) {
g := &optGenerator{}
opts := g.generate(optConfig{
cpuMetrics: []cpuMetricType{
cpuC7StateResidency,
},
msrReadTimeout: 0, // timeout disabled
})
require.Len(t, opts, 1)
withMsrUsed := false
for _, opt := range opts {
if strings.Contains(runtime.FuncForPC(reflect.ValueOf(opt).Pointer()).Name(), ".WithMsr.") {
withMsrUsed = true
continue
}
}
require.True(t, withMsrUsed, "WithMsr wasn't included in the generated options")
})
t.Run("WithLogger", func(t *testing.T) {
g := &optGenerator{}
opts := g.generate(optConfig{
cpuMetrics: []cpuMetricType{
cpuC3StateResidency,
},
log: &testutil.Logger{},
})
require.Len(t, opts, 2)
withLoggerUsed := false
for _, opt := range opts {
if strings.Contains(runtime.FuncForPC(reflect.ValueOf(opt).Pointer()).Name(), ".WithLogger.") {
withLoggerUsed = true
continue
}
}
require.True(t, withLoggerUsed, "WithLogger wasn't included in the generated options")
})
}
func TestNeedsMsrPackage(t *testing.T) {
packageMetrics := []packageMetricType{
packageThermalDesignPower, // needs rapl
packageCurrentDramPowerConsumption, // needs rapl
packageMetricType(420),
}
t.Run("False", func(t *testing.T) {
require.False(t, needsMsrPackage(packageMetrics))
})
t.Run("True", func(t *testing.T) {
t.Run("CPUBaseFreq", func(t *testing.T) {
packageMetrics[len(packageMetrics)-1] = packageCPUBaseFrequency
require.True(t, needsMsrPackage(packageMetrics))
})
t.Run("PackageTurboLimit", func(t *testing.T) {
packageMetrics[len(packageMetrics)-1] = packageTurboLimit
require.True(t, needsMsrPackage(packageMetrics))
})
t.Run("PackageUncoreFrequency", func(t *testing.T) {
packageMetrics[len(packageMetrics)-1] = packageUncoreFrequency
require.True(t, needsMsrPackage(packageMetrics))
})
})
}
func TestNeedsMsrCPU(t *testing.T) {
cpuMetrics := []cpuMetricType{
cpuFrequency, // needs cpuFreq
cpuC0SubstateC01Percent, // needs perf
}
t.Run("False", func(t *testing.T) {
require.False(t, needsMsrCPU(cpuMetrics))
})
t.Run("True", func(t *testing.T) {
t.Run("CPUTemperature", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuTemperature
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUC0StateResidency", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuC0StateResidency
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUC1StateResidency", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuC1StateResidency
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUC3StateResidency", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuC3StateResidency
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUC6StateResidency", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuC6StateResidency
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUC7StateResidency", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuC7StateResidency
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUBusyCycles", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuBusyCycles
require.True(t, needsMsrCPU(cpuMetrics))
})
t.Run("CPUBusyFrequency", func(t *testing.T) {
cpuMetrics[len(cpuMetrics)-1] = cpuBusyFrequency
require.True(t, needsMsrCPU(cpuMetrics))
})
})
}
func TestNeedsRapl(t *testing.T) {
metrics := []packageMetricType{
packageCPUBaseFrequency, // needs msr
packageUncoreFrequency, // needs uncoreFreq
packageMetricType(420),
}
t.Run("False", func(t *testing.T) {
require.False(t, needsRapl(metrics))
})
t.Run("True", func(t *testing.T) {
t.Run("PackageCurrentPowerConsumption", func(t *testing.T) {
metrics[len(metrics)-1] = packageCurrentPowerConsumption
require.True(t, needsRapl(metrics))
})
t.Run("PackageCurrentDramPowerConsumption", func(t *testing.T) {
metrics[len(metrics)-1] = packageCurrentDramPowerConsumption
require.True(t, needsRapl(metrics))
})
t.Run("PackageThermalDesignPower", func(t *testing.T) {
metrics[len(metrics)-1] = packageThermalDesignPower
require.True(t, needsRapl(metrics))
})
})
}
func TestNeedsCoreFreq(t *testing.T) {
metrics := []cpuMetricType{
cpuTemperature, // needs msr
cpuC1StateResidency, // needs msr
cpuC0SubstateC01Percent, // needs perf
cpuMetricType(420),
}
t.Run("False", func(t *testing.T) {
require.False(t, needsCoreFreq(metrics))
})
t.Run("True", func(t *testing.T) {
metrics[len(metrics)-1] = cpuFrequency
require.True(t, needsCoreFreq(metrics))
})
}
func TestNeedsUncoreFreq(t *testing.T) {
metrics := []packageMetricType{
packageCPUBaseFrequency, // needs msr
packageThermalDesignPower, // needs rapl
packageMetricType(420),
}
t.Run("False", func(t *testing.T) {
require.False(t, needsUncoreFreq(metrics))
})
t.Run("True", func(t *testing.T) {
metrics[len(metrics)-1] = packageUncoreFrequency
require.True(t, needsUncoreFreq(metrics))
})
}
func TestNeedsPerf(t *testing.T) {
metrics := []cpuMetricType{
cpuFrequency, // needs cpuFreq
cpuC1StateResidency, // needs msr
cpuMetricType(420),
}
t.Run("False", func(t *testing.T) {
require.False(t, needsPerf(metrics))
})
t.Run("True", func(t *testing.T) {
t.Run("CPUC0SubstateC01Percent", func(t *testing.T) {
metrics[len(metrics)-1] = cpuC0SubstateC01Percent
require.True(t, needsPerf(metrics))
})
t.Run("CPUC0SubstateC02Percent", func(t *testing.T) {
metrics[len(metrics)-1] = cpuC0SubstateC02Percent
require.True(t, needsPerf(metrics))
})
t.Run("CPUC0SubstateC0WaitPercent", func(t *testing.T) {
metrics[len(metrics)-1] = cpuC0SubstateC0WaitPercent
require.True(t, needsPerf(metrics))
})
})
}

48
plugins/inputs/intel_powerstat/sample.conf Normal file
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# Intel PowerStat plugin enables monitoring of platform metrics (power, TDP)
# and per-CPU metrics like temperature, power and utilization. Please see the
# plugin readme for details on software and hardware compatibility.
# This plugin ONLY supports Linux.
[[inputs.intel_powerstat]]
## The user can choose which package metrics are monitored by the plugin with
## the package_metrics setting:
## - The default, will collect "current_power_consumption",
## "current_dram_power_consumption" and "thermal_design_power".
## - Leaving this setting empty means no package metrics will be collected.
## - Finally, a user can specify individual metrics to capture from the
## supported options list.
## Supported options:
## "current_power_consumption", "current_dram_power_consumption",
## "thermal_design_power", "max_turbo_frequency", "uncore_frequency",
## "cpu_base_frequency"
# package_metrics = ["current_power_consumption", "current_dram_power_consumption", "thermal_design_power"]
## The user can choose which per-CPU metrics are monitored by the plugin in
## cpu_metrics array.
## Empty or missing array means no per-CPU specific metrics will be collected
## by the plugin.
## Supported options:
## "cpu_frequency", "cpu_c0_state_residency", "cpu_c1_state_residency",
## "cpu_c3_state_residency", "cpu_c6_state_residency", "cpu_c7_state_residency",
## "cpu_temperature", "cpu_busy_frequency", "cpu_c0_substate_c01",
## "cpu_c0_substate_c02", "cpu_c0_substate_c0_wait"
# cpu_metrics = []
## CPUs metrics to include from those configured in cpu_metrics array
## Can't be combined with excluded_cpus. Empty means all CPUs are gathered.
## e.g. ["0-3", "4,5,6"] or ["1-3,4"]
# included_cpus = []
## CPUs metrics to exclude from those configured in cpu_metrics array
## Can't be combined with included_cpus. Empty means all CPUs are gathered.
## e.g. ["0-3", "4,5,6"] or ["1-3,4"]
# excluded_cpus = []
## Filesystem location of JSON file that contains PMU event definitions.
## Mandatory only for perf-related metrics (cpu_c0_substate_c01, cpu_c0_substate_c02, cpu_c0_substate_c0_wait).
# event_definitions = ""
## The user can set the timeout duration for MSR reading.
## Enabling this timeout can be useful in situations where, on heavily loaded systems,
## the code waits too long for a kernel response to MSR read requests.
## 0 disables the timeout (default).
# msr_read_timeout = "0ms"

27
plugins/inputs/intel_powerstat/testdata/aperfmperf_flag_not_found/cpuinfo vendored Normal file
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@ -0,0 +1,27 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

26
plugins/inputs/intel_powerstat/testdata/cpu_model_missing/cpuinfo vendored Normal file
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@ -0,0 +1,26 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

111
plugins/inputs/intel_powerstat/testdata/cpuinfo vendored Normal file
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@ -0,0 +1,111 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 1
cpu cores : 56
apicid : 2
initial apicid : 2
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 2
cpu cores : 56
apicid : 4
initial apicid : 4
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 3
cpu cores : 56
apicid : 6
initial apicid : 6
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

27
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processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

27
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processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 14
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

27
plugins/inputs/intel_powerstat/testdata/msr_flag_not_found/cpuinfo vendored Normal file
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processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

299
plugins/inputs/intel_powerstat/testdata/sapphirerapids_core.json vendored Normal file
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
"DatePublished": "06/28/2023",
"Version": "1.15",
"Legend": ""
},
"Events": [
{
"EventCode": "0x00",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"BriefDescription": "Core cycles when the thread is not in halt state",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"Counter": "Fixed counter 1",
"PEBScounters": "33",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x00",
"UMask": "0x03",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"BriefDescription": "Reference cycles when the core is not in halt state.",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"Counter": "Fixed counter 2",
"PEBScounters": "34",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x00",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"BriefDescription": "Thread cycles when thread is not in halt state",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x01",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
"BriefDescription": "Reference cycles when the core is not in halt state.",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "25003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x08",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x10",
"EventName": "CPU_CLK_UNHALTED.C01",
"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x20",
"EventName": "CPU_CLK_UNHALTED.C02",
"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x40",
"EventName": "CPU_CLK_UNHALTED.PAUSE",
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
"PublicDescription": "CPU_CLK_UNHALTED.PAUSE",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x40",
"EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
"PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "1",
"Invert": "0",
"EdgeDetect": "1",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x70",
"EventName": "CPU_CLK_UNHALTED.C0_WAIT",
"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
}
]
}

25
plugins/inputs/intel_powerstat/testdata/vendor_not_supported/cpuinfo vendored Normal file
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processor : 0
vendor_id : AuthenticAMD
cpu family : 16
model : 2
model name : AMD Phenom(tm) 9550 Quad-Core Processor
stepping : 3
cpu MHz : 1100.000
cache size : 512 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc extd_apicid pni monitor cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs
bogomips : 4409.53
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 48 bits physical, 48 bits virtual
power management: ts ttp tm stc 100mhzsteps hwpstate