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Adding upstream version 1.34.4.

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Signed-off-by: Daniel Baumann <daniel@debian.org>
This commit is contained in:
Daniel Baumann 2025-05-24 07:26:29 +02:00
parent e393c3af3f
commit 4978089aab
Signed by: daniel
GPG key ID: FBB4F0E80A80222F
4963 changed files with 677545 additions and 0 deletions
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27
plugins/inputs/intel_powerstat/testdata/aperfmperf_flag_not_found/cpuinfo vendored Normal file
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@ -0,0 +1,27 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

26
plugins/inputs/intel_powerstat/testdata/cpu_model_missing/cpuinfo vendored Normal file
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@ -0,0 +1,26 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

111
plugins/inputs/intel_powerstat/testdata/cpuinfo vendored Normal file
View file

@ -0,0 +1,111 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 1
cpu cores : 56
apicid : 2
initial apicid : 2
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 2
cpu cores : 56
apicid : 4
initial apicid : 4
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 3
cpu cores : 56
apicid : 6
initial apicid : 6
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

27
plugins/inputs/intel_powerstat/testdata/dts_flag_not_found/cpuinfo vendored Normal file
View file

@ -0,0 +1,27 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

27
plugins/inputs/intel_powerstat/testdata/model_not_supported/cpuinfo vendored Normal file
View file

@ -0,0 +1,27 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 14
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

27
plugins/inputs/intel_powerstat/testdata/msr_flag_not_found/cpuinfo vendored Normal file
View file

@ -0,0 +1,27 @@
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 143
model name : Intel(R) Xeon(R) Platinum 8480+
stepping : 8
microcode : 0xab0000c0
cpu MHz : 2000.000
cache size : 107520 KB
physical id : 0
siblings : 112
core id : 0
cpu cores : 56
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 32
wp : yes
flags : fpu vme de pse tsc pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling usr_wait_pause
bugs : spectre_v1 spectre_v2 spec_store_bypass swapgs eibrs_pbrsb
bogomips : 4000.00
clflush size : 64
cache_alignment : 64
address sizes : 52 bits physical, 57 bits virtual
power management:

299
plugins/inputs/intel_powerstat/testdata/sapphirerapids_core.json vendored Normal file
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
"DatePublished": "06/28/2023",
"Version": "1.15",
"Legend": ""
},
"Events": [
{
"EventCode": "0x00",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"BriefDescription": "Core cycles when the thread is not in halt state",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"Counter": "Fixed counter 1",
"PEBScounters": "33",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x00",
"UMask": "0x03",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"BriefDescription": "Reference cycles when the core is not in halt state.",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"Counter": "Fixed counter 2",
"PEBScounters": "34",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x00",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"BriefDescription": "Thread cycles when thread is not in halt state",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x01",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
"BriefDescription": "Reference cycles when the core is not in halt state.",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "25003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0x3c",
"UMask": "0x08",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x10",
"EventName": "CPU_CLK_UNHALTED.C01",
"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x20",
"EventName": "CPU_CLK_UNHALTED.C02",
"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x40",
"EventName": "CPU_CLK_UNHALTED.PAUSE",
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
"PublicDescription": "CPU_CLK_UNHALTED.PAUSE",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x40",
"EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
"PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "1",
"Invert": "0",
"EdgeDetect": "1",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
},
{
"EventCode": "0xec",
"UMask": "0x70",
"EventName": "CPU_CLK_UNHALTED.C0_WAIT",
"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Speculative": "1"
}
]
}

25
plugins/inputs/intel_powerstat/testdata/vendor_not_supported/cpuinfo vendored Normal file
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processor : 0
vendor_id : AuthenticAMD
cpu family : 16
model : 2
model name : AMD Phenom(tm) 9550 Quad-Core Processor
stepping : 3
cpu MHz : 1100.000
cache size : 512 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nonstop_tsc extd_apicid pni monitor cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs
bogomips : 4409.53
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 48 bits physical, 48 bits virtual
power management: ts ttp tm stc 100mhzsteps hwpstate