252 lines
4.6 KiB
Groff
252 lines
4.6 KiB
Groff
.TH "libnvme" 9 "enum nvme_cap" "November 2024" "API Manual" LINUX
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.SH NAME
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enum nvme_cap \- This field indicates the controller capabilities register
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.SH SYNOPSIS
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enum nvme_cap {
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.br
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.BI " NVME_CAP_MQES_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_CQR_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_AMS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_TO_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_DSTRD_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_NSSRC_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_CSS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_BPS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_CPS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_MPSMIN_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_MPSMAX_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_PMRS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_CMBS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_NSSS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_CRMS_SHIFT"
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,
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.br
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.br
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.BI " NVME_CAP_MQES_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_CQR_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_AMS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_TO_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_DSTRD_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_NSSRC_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_CSS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_BPS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_CPS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_MPSMIN_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_MPSMAX_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_PMRS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_CMBS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_NSSS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_CRMS_MASK"
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,
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.br
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.br
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.BI " NVME_CAP_AMS_WRR"
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,
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.br
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.br
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.BI " NVME_CAP_AMS_VS"
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,
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.br
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.br
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.BI " NVME_CAP_CSS_NVM"
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,
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.br
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.br
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.BI " NVME_CAP_CSS_CSI"
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,
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.br
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.br
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.BI " NVME_CAP_CSS_ADMIN"
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,
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.br
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.br
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.BI " NVME_CAP_CPS_NONE"
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,
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.br
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.br
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.BI " NVME_CAP_CPS_CTRL"
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,
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.br
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.br
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.BI " NVME_CAP_CPS_DOMAIN"
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,
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.br
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.br
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.BI " NVME_CAP_CPS_NVMS"
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,
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.br
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.br
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.BI " NVME_CAP_CRWMS"
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,
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.br
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.br
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.BI " NVME_CAP_CRIMS"
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};
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.SH Constants
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.IP "NVME_CAP_MQES_SHIFT" 12
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Shift amount to get the maximum queue entries supported
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.IP "NVME_CAP_CQR_SHIFT" 12
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Shift amount to get the contiguous queues required
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.IP "NVME_CAP_AMS_SHIFT" 12
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Shift amount to get the arbitration mechanism supported
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.IP "NVME_CAP_TO_SHIFT" 12
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Shift amount to get the timeout
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.IP "NVME_CAP_DSTRD_SHIFT" 12
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Shift amount to get the doorbell stride
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.IP "NVME_CAP_NSSRC_SHIFT" 12
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Shift amount to get the NVM subsystem reset supported
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.IP "NVME_CAP_CSS_SHIFT" 12
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Shift amount to get the command sets supported
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.IP "NVME_CAP_BPS_SHIFT" 12
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Shift amount to get the boot partition support
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.IP "NVME_CAP_CPS_SHIFT" 12
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Shift amount to get the controller power scope
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.IP "NVME_CAP_MPSMIN_SHIFT" 12
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Shift amount to get the memory page size minimum
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.IP "NVME_CAP_MPSMAX_SHIFT" 12
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Shift amount to get the memory page size maximum
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.IP "NVME_CAP_PMRS_SHIFT" 12
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Shift amount to get the persistent memory region supported
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.IP "NVME_CAP_CMBS_SHIFT" 12
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Shift amount to get the controller memory buffer supported
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.IP "NVME_CAP_NSSS_SHIFT" 12
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Shift amount to get the NVM subsystem shutdown supported
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.IP "NVME_CAP_CRMS_SHIFT" 12
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Shift amount to get the controller ready modes supported
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.IP "NVME_CAP_MQES_MASK" 12
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Mask to get the maximum queue entries supported
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.IP "NVME_CAP_CQR_MASK" 12
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Mask to get the contiguous queues required
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.IP "NVME_CAP_AMS_MASK" 12
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Mask to get the arbitration mechanism supported
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.IP "NVME_CAP_TO_MASK" 12
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Mask to get the timeout
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.IP "NVME_CAP_DSTRD_MASK" 12
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Mask to get the doorbell stride
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.IP "NVME_CAP_NSSRC_MASK" 12
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Mask to get the NVM subsystem reset supported
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.IP "NVME_CAP_CSS_MASK" 12
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Mask to get the command sets supported
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.IP "NVME_CAP_BPS_MASK" 12
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Mask to get the boot partition support
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.IP "NVME_CAP_CPS_MASK" 12
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Mask to get the controller power scope
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.IP "NVME_CAP_MPSMIN_MASK" 12
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Mask to get the memory page size minimum
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.IP "NVME_CAP_MPSMAX_MASK" 12
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Mask to get the memory page size maximum
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.IP "NVME_CAP_PMRS_MASK" 12
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Mask to get the persistent memory region supported
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.IP "NVME_CAP_CMBS_MASK" 12
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Mask to get the controller memory buffer supported
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.IP "NVME_CAP_NSSS_MASK" 12
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Mask to get the NVM subsystem shutdown supported
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.IP "NVME_CAP_CRMS_MASK" 12
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Mask to get the controller ready modes supported
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.IP "NVME_CAP_AMS_WRR" 12
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Weighted round robin with urgent priority class
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.IP "NVME_CAP_AMS_VS" 12
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Vendor specific
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.IP "NVME_CAP_CSS_NVM" 12
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NVM command set or a discovery controller
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.IP "NVME_CAP_CSS_CSI" 12
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Controller supports one or more I/O command sets
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.IP "NVME_CAP_CSS_ADMIN" 12
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No I/O command set is supported
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.IP "NVME_CAP_CPS_NONE" 12
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Not reported
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.IP "NVME_CAP_CPS_CTRL" 12
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Controller scope
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.IP "NVME_CAP_CPS_DOMAIN" 12
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Domain scope
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.IP "NVME_CAP_CPS_NVMS" 12
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NVM subsystem scope
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.IP "NVME_CAP_CRWMS" 12
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Controller ready with media support
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.IP "NVME_CAP_CRIMS" 12
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Controller ready independent of media support
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