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Merging upstream version 1.12.

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Signed-off-by: Daniel Baumann <daniel@debian.org>
This commit is contained in:
Daniel Baumann 2025-03-20 08:08:33 +01:00
parent 8d543389aa
commit a3d0cc5ebd
Signed by: daniel
GPG key ID: FBB4F0E80A80222F
1005 changed files with 9469 additions and 1830 deletions
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142
doc/man/nvme_feat.2
View file

@ -1,4 +1,4 @@
.TH "libnvme" 9 "enum nvme_feat" "November 2024" "API Manual" LINUX
.TH "libnvme" 9 "enum nvme_feat" "March 2025" "API Manual" LINUX
.SH NAME
enum nvme_feat \- Features Access Shifts/Masks values
.SH SYNOPSIS
@ -228,6 +228,86 @@ enum nvme_feat {
,
.br
.br
.BI " NVME_FEAT_AE_NNSSHDN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_NNSSHDN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_TTHRY_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_TTHRY_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_RASSN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_RASSN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_RGRP0_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_RGRP0_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_ANSAN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_ANSAN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_ZDCN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_ZDCN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_PMDRLPCN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_PMDRLPCN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_ADLPCN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_ADLPCN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_HDLPCN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_HDLPCN_MASK"
,
.br
.br
.BI " NVME_FEAT_AE_DLPCN_SHIFT"
,
.br
.br
.BI " NVME_FEAT_AE_DLPCN_MASK"
,
.br
.br
.BI " NVME_FEAT_APST_APSTE_SHIFT"
,
.br
@ -332,6 +412,22 @@ enum nvme_feat {
,
.br
.br
.BI " NVME_FEAT_FDPE_PHNDL_SHIFT"
,
.br
.br
.BI " NVME_FEAT_FDPE_PHNDL_MASK"
,
.br
.br
.BI " NVME_FEAT_FDPE_NOET_SHIFT"
,
.br
.br
.BI " NVME_FEAT_FDPE_NOET_MASK"
,
.br
.br
.BI " NVME_FEAT_SPM_PBSLC_SHIFT"
,
.br
@ -396,6 +492,22 @@ enum nvme_feat {
,
.br
.br
.BI " NVME_FEAT_SPINUP_CONTROL_SHIFT"
,
.br
.br
.BI " NVME_FEAT_SPINUP_CONTROL_MASK"
,
.br
.br
.BI " NVME_FEAT_PLS_MODE_SHIFT"
,
.br
.br
.BI " NVME_FEAT_PLS_MODE_MASK"
,
.br
.br
.BI " NVME_FEAT_FDP_ENABLED_SHIFT"
,
.br
@ -476,6 +588,26 @@ enum nvme_feat {
.IP "NVME_FEAT_AE_LBAS_MASK" 12
.IP "NVME_FEAT_AE_EGA_SHIFT" 12
.IP "NVME_FEAT_AE_EGA_MASK" 12
.IP "NVME_FEAT_AE_NNSSHDN_SHIFT" 12
.IP "NVME_FEAT_AE_NNSSHDN_MASK" 12
.IP "NVME_FEAT_AE_TTHRY_SHIFT" 12
.IP "NVME_FEAT_AE_TTHRY_MASK" 12
.IP "NVME_FEAT_AE_RASSN_SHIFT" 12
.IP "NVME_FEAT_AE_RASSN_MASK" 12
.IP "NVME_FEAT_AE_RGRP0_SHIFT" 12
.IP "NVME_FEAT_AE_RGRP0_MASK" 12
.IP "NVME_FEAT_AE_ANSAN_SHIFT" 12
.IP "NVME_FEAT_AE_ANSAN_MASK" 12
.IP "NVME_FEAT_AE_ZDCN_SHIFT" 12
.IP "NVME_FEAT_AE_ZDCN_MASK" 12
.IP "NVME_FEAT_AE_PMDRLPCN_SHIFT" 12
.IP "NVME_FEAT_AE_PMDRLPCN_MASK" 12
.IP "NVME_FEAT_AE_ADLPCN_SHIFT" 12
.IP "NVME_FEAT_AE_ADLPCN_MASK" 12
.IP "NVME_FEAT_AE_HDLPCN_SHIFT" 12
.IP "NVME_FEAT_AE_HDLPCN_MASK" 12
.IP "NVME_FEAT_AE_DLPCN_SHIFT" 12
.IP "NVME_FEAT_AE_DLPCN_MASK" 12
.IP "NVME_FEAT_APST_APSTE_SHIFT" 12
.IP "NVME_FEAT_APST_APSTE_MASK" 12
.IP "NVME_FEAT_HMEM_EHM_SHIFT" 12
@ -502,6 +634,10 @@ enum nvme_feat {
.IP "NVME_FEAT_EG_ENDGID_MASK" 12
.IP "NVME_FEAT_EG_EGCW_SHIFT" 12
.IP "NVME_FEAT_EG_EGCW_MASK" 12
.IP "NVME_FEAT_FDPE_PHNDL_SHIFT" 12
.IP "NVME_FEAT_FDPE_PHNDL_MASK" 12
.IP "NVME_FEAT_FDPE_NOET_SHIFT" 12
.IP "NVME_FEAT_FDPE_NOET_MASK" 12
.IP "NVME_FEAT_SPM_PBSLC_SHIFT" 12
.IP "NVME_FEAT_SPM_PBSLC_MASK" 12
.IP "NVME_FEAT_HOSTID_EXHID_SHIFT" 12
@ -518,6 +654,10 @@ enum nvme_feat {
.IP "NVME_FEAT_WP_WPS_MASK" 12
.IP "NVME_FEAT_IOCSP_IOCSCI_SHIFT" 12
.IP "NVME_FEAT_IOCSP_IOCSCI_MASK" 12
.IP "NVME_FEAT_SPINUP_CONTROL_SHIFT" 12
.IP "NVME_FEAT_SPINUP_CONTROL_MASK" 12
.IP "NVME_FEAT_PLS_MODE_SHIFT" 12
.IP "NVME_FEAT_PLS_MODE_MASK" 12
.IP "NVME_FEAT_FDP_ENABLED_SHIFT" 12
.IP "NVME_FEAT_FDP_ENABLED_MASK" 12
.IP "NVME_FEAT_FDP_INDEX_SHIFT" 12