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Merging upstream version 1.12.

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Signed-off-by: Daniel Baumann <daniel@debian.org>
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Daniel Baumann 2025-03-20 08:08:33 +01:00
parent 8d543389aa
commit a3d0cc5ebd
Signed by: daniel
GPG key ID: FBB4F0E80A80222F
1005 changed files with 9469 additions and 1830 deletions
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doc/man/nvme_lm_queue_attributes.2 Normal file
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.TH "libnvme" 9 "enum nvme_lm_queue_attributes" "March 2025" "API Manual" LINUX
.SH NAME
enum nvme_lm_queue_attributes \- I/O Submission and I/O Completion Queue Attributes
.SH SYNOPSIS
enum nvme_lm_queue_attributes {
.br
.BI " NVME_LM_IOSQPC_MASK"
,
.br
.br
.BI " NVME_LM_IOSQPC_SHIFT"
,
.br
.br
.BI " NVME_LM_IOSQPRIO_MASK"
,
.br
.br
.BI " NVME_LM_IOSQPRIO_SHIFT"
,
.br
.br
.BI " NVME_LM_IOCQPC_MASK"
,
.br
.br
.BI " NVME_LM_IOCQPC_SHIFT"
,
.br
.br
.BI " NVME_LM_IOCQIEN_MASK"
,
.br
.br
.BI " NVME_LM_IOCQIEN_SHIFT"
,
.br
.br
.BI " NVME_LM_S0PT_MASK"
,
.br
.br
.BI " NVME_LM_S0PT_SHIFT"
,
.br
.br
.BI " NVME_LM_IOCQIV_MASK"
,
.br
.br
.BI " NVME_LM_IOCQIV_SHIFT"
};
.SH Constants
.IP "NVME_LM_IOSQPC_MASK" 12
Mask to get the Physically Contiguous (PC) bit for this I/O
submission queue.
.IP "NVME_LM_IOSQPC_SHIFT" 12
Shift to get the PC bit for this I/O submission queue
.IP "NVME_LM_IOSQPRIO_MASK" 12
Mask to get the Priority for this I/O submission queue.
.IP "NVME_LM_IOSQPRIO_SHIFT" 12
Shift to get the Priority for this I/O submission queue.
.IP "NVME_LM_IOCQPC_MASK" 12
Mask to get the Physicaly Contiguous (PC) bit for this I/O
completion queue.
.IP "NVME_LM_IOCQPC_SHIFT" 12
Shift to get the PC bit for this I/O completion queue.
.IP "NVME_LM_IOCQIEN_MASK" 12
Mask to get the Interrupts Enabled bit for this I/O completion
queue
.IP "NVME_LM_IOCQIEN_SHIFT" 12
Shift to get the Interrupts Enabled bit for this I/O completion
.IP "NVME_LM_S0PT_MASK" 12
Mask to get the value of the Phase Tag bit for Slot 0 of this I/O
completion queue.
.IP "NVME_LM_S0PT_SHIFT" 12
Shift to get the value of the Phase Tag bit for Slot 0 of this I/O
completion queue.
.IP "NVME_LM_IOCQIV_MASK" 12
Mask to get the Interrupt Vector (IV) for this I/O completion
queue.
.IP "NVME_LM_IOCQIV_SHIFT" 12
Shift to get the IV for this I/O completion queue.